PIC16C711-20/SO【PDF 57/177 页】IC MCU OTP 1KX14 A/D 18SOIC

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Sheet目录3861

53页 54页 55页 56页 [57页]58页 59页 60页 61页

1997 Microchip Technology Inc.

DS30272A-page 15

PIC16C71X

TABLE 4-2:

PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR, PER

Value on all

other resets

(3)

Bank 0

00h(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

01h

TMR0

Timer0 module’s register

xxxx xxxx

uuuu uuuu

02h(1)

PCL

Program Counter's (PC) Least Signicant Byte

0000 0000

03h(1)

STATUS

IRP(4)

RP1(4)

RP0

0001 1xxx

000q quuu

04h(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

05h

PORTA

—

PORTA Data Latch when written: PORTA pins when read

---x 0000

---u 0000

06h

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

uuuu uuuu

07h

—

Unimplemented

—

08h

—

Unimplemented

—

09h

—

Unimplemented

—

0Ah(1,2)

PCLATH

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

0Bh(1)

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

—

ADIF

—

-0-- ----

0Dh

—

Unimplemented

—

0Eh

—

Unimplemented

—

0Fh

—

Unimplemented

—

10h

—

Unimplemented

—

11h

—

Unimplemented

—

12h

—

Unimplemented

—

13h

—

Unimplemented

—

14h

—

Unimplemented

—

15h

—

Unimplemented

—

16h

—

Unimplemented

—

17h

—

Unimplemented

—

18h

—

Unimplemented

—

19h

—

Unimplemented

—

1Ah

—

Unimplemented

—

1Bh

—

Unimplemented

—

1Ch

—

Unimplemented

—

1Dh

—

Unimplemented

—

1Eh

ADRES

A/D Result Register

xxxx xxxx

uuuu uuuu

1Fh

ADCON0

ADCS1

ADCS0

CHS2

CHS1

CHS0

GO/DONE

—

ADON

0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1:

These registers can be addressed from either bank.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

The IRP and RP1 bits are reserved on the PIC16C715, always maintain these bits clear.

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